1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, the present invention relates to a semiconductor memory device having floating body memory cells and a method of operating the same.
2. Description of Related Art
In general, a dynamic random access memory (DRAM) device, which is one type of semiconductor memory device, includes a dynamic memory cell that includes a transistor and a capacitor, such that data “0” or “1” is determined depending on whether or not the capacitor is charged with electric charges. Since electric charges charged in the capacitor are lost in a predetermined amount of time, a refresh operation is necessary.
However, because the conventional dynamic memory cell depends on the capacitor, when a memory cell array includes such dynamic memory cells, there is a limit in reducing the physical layout area of the semiconductor memory device.
For this reason, use of a transistor having a floating body has been recently proposed. The transistor stores many carriers in the floating body, and needs to be refreshed because the stored carriers are lost in a predetermined amount of time. Therefore, although a memory cell having the floating body transistor does not include a capacitor, unlike a typical memory cell, the memory cell having the floating body transistor operates in effectively the same manner as the capacitor in order to function as a dynamic memory cell.
As described above, the floating body transistor may constitute a memory cell without using a capacitor. Thus, assuming that a semiconductor memory device having the same capacity is fabricated using each of the two different kinds of memory cells (i.e., the typical memory cell having one transistor and one capacitor, and the memory cell having the floating body transistor), the layout area of a semiconductor memory device including the memory cell having the floating body transistor can be smaller than that of a semiconductor memory device having the typical memory cell.
FIG. 1 illustrates the construction of a conventional memory device including a memory cell having a floating body transistor.
Referring to FIG. 1, the semiconductor memory device includes memory cell array blocks BLK1 and BLK2, bit line selectors 10-11 to 10-1m and 10-21 to 10-2m, reference bit line selectors 12-1 and 12-2, level limiters 14-1 to 14-m, and 14-(m+1), sense amplifiers 16-1 to 16-m, a reference voltage generator 18, comparators COM1 to COMm, latches LA1 to LAm, write back gates WBG1 to WBGm, read column selection gates RG1 to RGm, write column selection gates WG1 to WGm, and a reference write column selection gate RWG.
An operation of writing data to reference memory cells RMC of the semiconductor memory device shown in FIG. 1 will be described.
When a word line WL11 is enabled, a voltage of about 1.5 V is applied and a reference bit line selection signal RBS1 is enabled, a reference bit line RBL1 is connected to a reference sense bit line RSBL. When a reference write column selection signal RWCSL is enabled, an NMOS transistor N7 is turned on so that data transmitted to a write data line WD is transmitted through the reference sense bit line RSBL to the reference bit line RBL1.
At this time, when write data has a voltage of about −1.5 V, data “0” is written to the reference memory cell RMC connected between the word line WL11 and the reference bit line RBL1. In this process, data “0” is written to all reference memory cells RMC connected between the remaining word lines WL12 to WL1n and the reference bit line RBL1. Additionally, data “1” is written to all reference memory cells RMC connected between word lines WL11 to WL1n and WL21 to WL2n and a reference bit line RBL2. In this case, write data has a voltage of about 1.5 V.
In other words, data “0” is written to the reference memory cells RMC connected to a reference bit line RBL1 of each of the reference memory cell array blocks RBLK1 and RBLK2, while data “1” is written to the reference memory cells RMC connected to a reference bit line RBL2 thereof. Thus, the reference memory cells RMC are used to generate a reference voltage VREF in a read operation.
Next, an operation of writing data to memory cells MC will be described.
When a voltage of about 1.5 V is applied to the word line WL11, and a bit line selection signal BS1 is enabled, a bit line BL1 is connected to a sense bit line SBL1. When a write column selection signal WCSL1 is enabled, an NMOS transistor N6 is turned on. At this time, when a voltage of about −1.5 V is applied to the write data line WD, the voltage of about −1.5V is transmitted through the sense bit line SBL1 to the bit line BL1, so that data “0” is written to a memory cell MC connected between the word line WL1 and the bit line BL1. On the other hand, when a voltage of about 1.5 V is applied to the write data line WD, data “1” is written to the memory cell MC connected between the word line WL1 and the bit line BL1. In this process, a write operation is performed on all the memory cells MC.
Next, an operation of reading data from the memory cells MC will be described.
When a voltage of about 1.5 V is applied to the word line WL11 and the bit line selection signal BS1 is enabled, the bit line BL1 is connected to the sense bit line SBL1, and a signal is transmitted from the bit line BL1 to the sense bit line SBL1. The reference bit line selection signals RBS1 and RBS2 are enabled at the same time, and thus the reference bit lines RBL1 and RBL2 are connected to the reference sense bit line RSBL, and a signal is transmitted from the reference bit lines RBL1 and RBL2 to the reference sense bit line RSBL.
When a voltage of the sense bit line SBL1 due to a current supplied to the sense bit line SBL1 is at a higher level than a restricted voltage VBLR, the level limiter 14-1 prevents the flow of current from an output node al to the sense bit line SBL1, such that the voltage of the sense bit line SBL1 remains below the level of the restricted voltage VBLR, and generates a current Ic1 corresponding to data stored in the memory cell MC. When a voltage of the reference sense bit line RSBL is at a higher level than the restricted voltage VBLR due to a current supplied to the reference sense bit line RSBL, the level limiter 14-(m+1) prevents the flow of current from an output node a(m+1) to the reference sense bit line RSBL, such that the voltage of the reference sense bit line RSBL remains below the level of the restricted voltage VBLR, and generates a current Ic(m+1) corresponding to data stored in the reference memory cell RMC.
The sense amplifier 16-1 senses the current Ic1 and generates a sensing voltage Sn1. The reference voltage generator 18 senses the current Ic(m+1) and generates a reference voltage VREF. The comparator COM1 is enabled in response to a sense amplifier enable signal SEN, compares the sensing voltage output from the sense amplifier 16-1 with the reference voltage VREF and generates sensing data. Specifically, the comparator COM1 outputs a high-level signal to the corresponding node “a” when the sensing voltage Sn1 output from the sense amplifier 16-1 is at a lower level than the reference voltage VREF, and outputs a low-level signal to the corresponding node “a” when the sensing voltage Sn1 is at a higher level than the reference voltage VREF.
The latch LA1 latches the sensing data, and when a read column selection signal RCSL1 is enabled, NMOS transistors N2 and N4 are turned on. At this time, when a voltage at the node “a” is at a high level, an NMOS transistor N5 is turned on and transmits low-level data to an inverted read data line RDB. On the other hand, when the voltage at a node “b” is at a high level, an NMOS transistor N3 is turned on and transmits the low-level data to a read data line RD. That is, the low-level data is transmitted to the read data line RD or the inverted read data line RDB during a read operation.
After the read operation is finished, when a write back signal WB is enabled, an NMOS transistor N1 is turned on, so that high-level data at the corresponding node “b” of the latch LA1 is transmitted to the sense bit line SBL1, and data in the sense bit line SBL1 is transmitted to the bit line BL1. As a result, a refresh operation is performed on the memory cell MC connected between the word line WL11 and the bit line BL1 and having data “1” stored therein. In this process, the read operation is performed on all the memory cells MC.
A conventional semiconductor memory device as shown in FIG. 1 is described, for example, in U.S. Patent Application Publication No. 2003/0231524. Other examples of semiconductor memory devices including memory cells and reference memory cells with floating body transistors are disclosed in U.S. Patent Application Publication No. 2005/0068807 and U.S. Pat. Nos. 6,567,330 and 6,882,008.
However, the conventional semiconductor memory device shown in FIG. 1, for example, must include the reference memory cells RMC for storing data “0” and the reference memory cells RMC for storing data “1” in order to perform the read operation. Although it is illustrated in FIG. 1 that the semiconductor memory device includes a single reference memory cell for each memory cell array block, the semiconductor memory device may include a single reference memory cell array block for a predetermined number of sub-memory cell array blocks.
Although the conventional semiconductor memory device is designed so that the reference memory cells RMC and the memory cells MC permit the flow of current corresponding to data “0” when the data “0” is read, and permit the flow of current corresponding to data “1” when the data “1” is read, the currents corresponding to the data “0” and “1” vary according to changes in fabrication process, voltage and temperature, so that a read data error may be caused in the reference memory cells RMC and the memory cells MC. That is, a difference may be made between a voltage output from the sense amplifier and the reference voltage VREF, may result in data “0” being read as data “1” and data “1” being read as data “0”. This is because the conventional semiconductor memory device senses a current difference between the bit line and the reference bit line during the data read operation.
Also, the conventional semiconductor memory device shown in FIG. 1 requires a complicated circuit configuration for the data read operation. For example, the conventional semiconductor memory device of FIG. 1 requires the level limiters, the sense amplifiers, the comparators and the latches, as shown in FIG. 1.
Furthermore, in the conventional semiconductor memory device shown in FIG. 1, a negative voltage of −1.5 V should be applied to the bit line in order to write data “0”. Therefore, the conventional semiconductor memory device requires a negative voltage generator for generating a negative voltage to be applied to the bit line during writing of data “0”.